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DS2165Q
16/24/32kbps ADPCM Processor
www.maxim-ic.com
FEATURES
Compresses/expands 64kbps PCM voice to/from either 32kbps, 24kbps, or 16kbps Dual fully independent channel architecture; device can be programmed to perform either: - two expansions - two compressions - one expansion and one compression Interconnects directly to combo-codec devices Input to output delay is less than 375ms Simple serial port used to configure the device On-board time-slot assigner-circuit (TSAC) function allows data to be input/output at various time slots Supports Channel Associated Signaling Each channel can be independently idled or placed into bypass Available hardware mode requires no host processor; ideal for voice storage applications Single +5V supply; low-power CMOS technology Available in 28-pin PLCC 3V operation version is available (DS2165QL)
PIN ASSIGNMENT (Top View)
TM1 TM0 RST NC VDD YIN CLKY NC A0 A1 A2 A3 A4 A5
5 6 7 8 9 10 11 12 13 14 15 16 17 18 4 3 2 1 28 27 26 25 24 23
DS2165Q
22 21 20 19

FSY YOUT CS SDI SCLK XOUT NC
DESCRIPTION
The DS2165Q ADPCM processor chip is a dedicated digital-signal-processing (DSP) chip that has been optimized to perform adaptive-differential pulse-code modulation (ADPCM) speech compression at three different rates. The chip can be programmed to compress (expand) 64kbps voice data down to (up from) either 32kbps, 24kbps, or 16kbps. The compression to 32kbps follows the algorithm specified by CCITT Recommendation G.721 (July 1986) and ANSI document T1.301 (April 1987). The compression to 24kbps follows ANSI document T1.303. The compression to 16kbps follows a proprietary algorithm developed by Dallas Semiconductor. The DS2165Q can switch compression algorithms on-the-fly. This allows the user to make maximum use of the available bandwidth on a dynamic basis.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: http://www.maxim-ic.com/errata. 1 of 17 070802
SPS MCLK VSS NC XIN CLKX FSX
28-Pin PLCC
DS2165Q
OVERVIEW
The DS2165Q contains three major functional blocks: a high performance (10 MIPS) DSP engine, two independent PCM interfaces (X and Y) that connect directly to serial time-division-multiplexed (TDM) backplanes, and a serial port that can configure the device on-the-fly by an external controller. A 10MHz master clock is required by the DSP engine. The DS2165Q can be configured to perform either two expansions, two compressions, or one expansion and one compression. The PCM/ADPCM data interfaces support data rates from 256kHz to 4.096MHz. Typically, the PCM data rates are 1.544MHz for m-law and 2.048MHz for A-law. Each channel on the device samples the serial input PCM or ADPCM bit stream during a user-programmed input time slot, processes the data and outputs the result during a userprogrammed output time slot. Each PCM interface has a control register that specifies functional characteristics (compress, expand, bypass, and idle), data format (m-law or A-law), and algorithm reset control. With the SPS pin strapped high, the software mode is enabled and the serial port can be used to configure the device. In this mode, a novel addressing scheme allows multiple devices to share a common 3-wire control bus, simplifying system-level interconnect. With SPS low, the hardware mode is enabled. This mode disables the serial port and maps certain control register bits to some of the address and serial port pins. Under the hardware mode, no external host controller is required and all PCM/ADPCM input and output time slots default to time slot 0.
HARDWARE RESET
RST allows the user to reset both channel algorithms and the contents of the internal registers. This pin
must be held low for at least 1ms on system power-up after the master clock is stable to ensure that the device has initialized properly. RST should also be asserted when changing to or from the hardware mode. RST clears all bits of the control register for both channels except the IPD bits; the IPD bits for both channels are set to 1.
SOFTWARE MODE
Connecting SPS high enables the software mode. In this mode, an external host controller writes configuration data to the DS2165Q by the serial port through inputs SCLK, SDI, and CS (Figure 2). Each write to the DS2165Q is either a 2-byte write or a 4-byte write. A 2-byte write consists of the address/command byte (ACB), followed by a byte to configure the control register (CR) for either the X or Y channel. The 4-byte write consists of the ACB, followed by a byte to configure the CR, and then 1 byte to set the input time slot and another byte to set the output time slot.
ADDRESS/COMMAND BYTE
In the software mode, the address/command byte is the first byte written to the serial port; it identifies which of the 64 possible ADPCM processors sharing the port wiring is to be updated. Address data must match that at inputs A0 to A5. If no match occurs, the device ignores the following configuration data. If an address match occurs, the next 3 bytes written are accepted as control, input and output time slot data. Bit ACB.6 determines which side (X or Y) of the device is to be updated. The PCM and ADPCM outputs are tri-stated during register updates.
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DS2165Q
CONTROL REGISTER
The control register establishes idle, algorithm reset, bypass, data format, and channel coding for the selected channel. The X-side and Y-side PCM interfaces can be independently disabled (output tri-stated) by IPD. When IPD is set for both channels, the device enters a low-power standby mode. In this mode, the serial port must not be operated faster than 39kHz. ALRST resets the algorithm coefficients for the selected channel to their initial values. ALRST is cleared by the device when the algorithm reset is complete.
Table 1. PIN DESCRIPTION
PIN 2 3 4 6 7 8 9 10 11 12 13 14 16 17 18 20 21 22 23 24 25 26 27 28 SYMBOL
RST
TYPE I I
FUNCTION Reset. A high-low-high transition resets the algorithm. The device should be reset on power-up and when changing to or from the hardware mode. Test Modes 0 and 1. Connect to VSS for normal operation.
TM0 TM1 A0 A1 A2 A3 A4 A5 SPS MCLK VSS XIN CLKX FSX XOUT SCLK SDI
CS
I
Address Select. A0 = LSB, A5 = MSB. Must match address/command word to enable the serial port.
I I -- I I I O I I I O I I I --
Serial Port Select. Connect to VDD to select the serial port; connect to VSS to select the hardware mode. Master Clock. 10MHz clock for the ADPCM processing engine; may be asynchronous to SCLK, CLKX, and CLKY. Signal Ground. 0V X Data In. Sampled on falling edge of CLKX during selected time slots. X Data Clock. Data clock for the X-side PCM interface; must be synchronous with FSX. X Frame Sync. 8kHz frame sync for the X-side PCM interface. X Data Output. Updated on rising edge of CLKX during selected time slots. Serial Data Clock. Used to write to the serial port registers. Serial Data In. Data for on-board control registers; sampled on the rising edge of SCLK. LSB sent first. Chip Select. Must be low to write to the serial port. Y Data Output. Updated on rising edge of CLKY during selected time slots. Y Frame Sync. 8kHz frame sync for the Y-side PCM interface. Y Data Clock. Data clock for the Y-side PCM interface; must be synchronous with FSY. Y Data In. Sampled on falling edge of CLKY during selected time slots. Positive Supply. 5.0V (3.0V for DS2165QL)
YOUT FSY CLKY YIN VDD
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DS2165Q
Figure 1. BLOCK DIAGRAM
Figure 2. SERIAL PORT WRITE
Note: A 2-byte write is shown. The bypass feature is enabled when BYP is set and IPD is cleared. During bypass, no expansion or compression occurs. Bypass operates on bytewide (8 bits) slots when CP/ EX is set and on nibble-wide (4 bits) slots when CP/ EX is cleared. A-law (U/ A = 0) and m-law (U/ A = 1) PCM coding is independently selected for the X and Y channels by CR.2. If BYP and IPD are cleared, then CP/ EX determines if the input data is to be compressed or expanded.
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DS2165Q
Figure 3. ADDRESS/COMMAND BYTE
(MSB) -- SYMBOL -- X/ Y A5 A4 A3 A2 A1 A0 X/ Y POSITION ACB.7 ACB.6 ACB.5 ACB.4 ACB.3 ACB.2 ACB.1 ACB.0 A5 A4 A3 FUNCTION Reserved. Must be 0 for proper operation X/Y Channel Select 0 = update channel Y characteristics 1 = update channel X characteristics MSB of device address -- -- -- -- LSB of device address A2 A1 (LSB) A0
Figure 4. CONTROL REGISTER
(MSB) AS0 SYMBOL AS0 AS1 IPD ALRST BYP (LSB) AS1 POSITION CR.7 CR.6 CR.5 CR.4 CR.3 CR.2 CR.1 CR.0 IPD ALRST BYP FUNCTION Algorithm Select 0 (Table 2) Algorithm Select 1 (Table 2) Idle and Power-Down 0 = channel enabled 1 = channel disabled (output tri-stated) Algorithm Reset 0 = normal operation 1 = reset algorithm for selected channel Bypass 0 = normal operation 1 = bypass selected channel Data Format 0 = A-law 1 = m-law Algorithm Select 2 (Table 2) Channel Coding 0 = expand (decode) selected channel 1 = compress (encode) selected channel
U/ A
AS2
CP/ EX
U/ A
AS2
CP/ EX
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DS2165Q
Table 2. ALGORITHM SELECT BITS
ALGORITHM SELECTED 64kbps to/from 32kbps 64kbps to/from 24kbps 64kbps to/from 16kbps AS2 0 1 1 AS1 0 1 0 AS0 0 1 1
Figure 5. INPUT TIME SLOT REGISTER
(MSB) -- SYMBOL -- -- D5 D4 D3 D2 D1 D0 --POSITION ITR.7 ITR.6 ITR.5 ITR.4 ITR.3 ITR.2 ITR.1 ITR.0 D5 D4 D3 FUNCTION Reserved. Must be 0 for proper operation Reserved. Must be 0 for proper operation MSB of input time slot register -- -- -- -- LSB of input time slot register D2 D1 (LSB) D0
Figure 6. OUTPUT TIME SLOT REGISTER
(MSB) -- SYMBOL -- -- D5 D4 D3 D2 D1 D0 -- POSITION OTR.7 OTR.6 OTR.5 OTR.4 OTR.3 OTR.2 OTR.1 OTR.0 D5 D4 D3 FUNCTION Reserved. Must be 0 for proper operation Reserved. Must be 0 for proper operation MSB of output time slot register -- -- -- -- LSB of output time slot register D2 D1 (LSB) D0
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DS2165Q
TIME SLOT ASSIGNMENT/ORGANIZATION
On-board counters establish when PCM and ADPCM I/O occur. The counters are programmed by the time slot registers. Time slot size (number of bits wide) is determined by the state of CP/ EX . The number of time slots available is determined by the state of both CP/ EX and U/ A (Figures 7 through 10). For example, if the X channel is set to compress (CP/ EX = 1) and it is set to expect m-law data (U/ A = 1), then the input port (XIN) is set up for 32 8-bit time slots and the output port (XOUT) is set up for 64 4-bit time slots. The time slot organization is not dependent on which algorithm has been selected. Note: Time slots are counted from the frame sync signal starting at the first rising edge of either CLKX or CLKY after the frame sync.
Figure 7. m-LAW PCM INTERFACE
Figure 8. m-LAW ADPCM INTERFACE
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DS2165Q
Figure 9. A-LAW PCM INTERFACE
Figure 10. A-LAW ADPCM INTERFACE
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DS2165Q
HARDWARE MODE
The hardware mode is intended for applications that do not have an external controller available or do not require the extended features offered by the serial port. Connecting the SPS pin to VSS disables the serial port, clears all internal register bits, and maps the IPD, U/ A , and CP/ EX bits for both channels to external bits (Table 3). In the hardware mode, both the input and output time slots default to time slot 0.
Table 3. HARDWARE MODE
PIN # 6 7 8 9 10 11 22 23 NAME A0 A1 A2 A3 A4 A5 SDI REGISTER LOCATION CP/ EX (Channel X) AS0/AS1/AS2 (Channel X and Y) U/ A (Channel X) CP/ EX (Channel Y) AS0/AS1/AS2 (Channel X and Y) U/ A (Channel Y) IPD (Channel Y) IPD (Channel X) FUNCTION Channel X Coding Configuration 0 = Expand 1 = Compress Algorithm Select (Table 4) Channel X Data Format 0 = A-law 1 = m-law Channel Y Coding Configuration 0 = Expand 1 = Compress Algorithm Select (Table 4) Channel Y Data Format 0 = A-law 1 = m-law Channel Y Idle Select 0 = Channel Active 1 = Channel Idle Channel X Idle Select 0 = Channel Active 1 = Channel Idle
CS
NOTES:
1) SCLK must be connected to VSS when the hardware mode is selected. 2) When both channels are idled, power consumption is significantly reduced. 3) The NIL powers up within 800ms after either channel is returned to active from an idle state.
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DS2165Q
Table 4. ALGORITHM SELECT FOR HARDWARE MODE
ALGORITHM 64kbps to/from 32kbps CONFIGURATION OF A1 AND A4 Connect both A1 and A4 to VSS. Hold A1 and A4 low during a hardware reset; take both A1 and A4 high after the RST pin has returned high (allow 3ms after RST returns high before taking A1 and A4 high). Connect both A1 and A4 to VDD.
64kpbs to/from 24kbps
64kbps to/from 16kbps
Figure 11. DS2165Q CONNECTION TO CODEC/FILTER
DS2165Q
Suggested Codec/Filters* TP305X National Semiconductor ETC505X STMicroelectronics MC1455XX Motorola, Inc. TCM29CXX Texas Instruments Incorporated HD44238C Hitachi *Other generic codec/filter devices can be substituted.
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DS2165Q
PCM AND ADPCM INPUT/OUTPUT
Since the organization of the input and output time slots on the DS2165Q does not depend on the algorithm selected, it always assumes that PCM input and output are in 8-bit bytes and that ADPCM input and output are in 4-bit bytes. Figure 12 demonstrates how the DS2165Q handles the I/O for the three different algorithms. In the figure, it is assumed that channel X is in the compression mode (CP/ EX = 1) and channel Y is in the expansion mode (CP/ EX = 0). Also, it is assumed that both the input and output time slots for both channels are set to 0.
Figure 12. PCM AND ADPCM I/O EXAMPLE
Note 1: The bit after the LSB in the 24kbps ADPCM output is only a 1 when the DS2165Q is operated in the software mode and is programmed to perform 24kbps compression; in all other configurations, it is a 0.
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DS2165Q
TIME SLOT RESTRICTIONS
Under certain conditions, the DS2165Q does contain some restrictions on the output time slots that are available. These restrictions are covered in detail in a separate application note. No restrictions occur if the DS2165Q is operated in the hardware mode.
INPUT TO OUTPUT DELAY
With all three compressions algorithms, the total delay, from the time the PCM data sample is captured by the DS2165Q to the time it is output, is always less than 375ms. The exact delay is determined by the input and output time slots selected for each channel.
CHANNEL ASSOCIATED SIGNALING
The DS2165Q supports Channel Associated Signaling (CAS) through its ability to automatically change from the 32kbps compression algorithm to the 24kbps algorithm. If the DS2165Q is configured to perform the 32kbps algorithm, then in both the hardware and software mode it senses the frame sync inputs (FSX and FSY) for a double-wide frame-sync pulse. Whenever the DS2165Q receives a doublewide pulse, it automatically switches from the 32kbps algorithm to the 24kbps algorithm. Switching to the 24kbps algorithm allows the user to insert signaling data into the LSB bit position of the ADPCM output because this bit does not contain any useful speech information.
ON-THE-FLY ALGORITHM SELECTION
In the software mode, the user can switch between the three available algorithms on-the-fly. That is, the DS2165Q does not need to be reset or stopped to make the change from one algorithm to another. The DS2165Q reads the control register before it starts to process each PCM or ADPCM sample. If the user wishes to switch algorithms, then the control register must be updated by the serial port before the first input sample to be processed with the new algorithm arrives at either XIN or YIN. The PCM and ACPCM outputs tri-state during register updates.
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DS2165Q
ABSOLUTE MAXIMUM RATINGS*
Voltage Range on Any Pin Relative to Ground Operating Temperature Range Storage Temperature Range Soldering Temperature Range -1.0V to +7.0V 0C to +70C -55C to +125C See IPC/JEDEC J-STD-020A
*This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER Logic 1 Logic 0 Supply Logic 1 Logic 0 Supply SYMBOL VIH VIL VDD VIH VIL VDD MIN 2.0 -0.3 4.5 2.2 -0.3 2.7 TYP MAX
(TA = 0C to +70C) UNITS V V V V V V NOTES 5, 7 5 5 6 6 6 (TA = +25C) VCC + 0.3 +0.8 5.5 VCC + 0.3 +0.4 3.6
CAPACITANCE
PARAMETER Input Capacitance Output Capacitance SYMBOL CIN COUT MIN TYP MAX 5 10
UNITS pF pF
NOTES
DC ELECTRICAL CHARACTERISTICS
PARAMETER Active Supply Current Active Supply Current Idle Supply Current Input Leakage Output Leakage Output Current (2.4V) Output Current (0.4V) Output Current (2.2V) Output Current (0.4V) SYMBOL IDDA IDDA IDDPD II IO IOH IOL IOH IOL
(VDD = 5V 10%, TA = 0C to +70C; VDD = 3.0V + 20% - 10% for DS2165QL) MIN TYP 20 12 1 -1.0 -1.0 -1.0 +4.0 -0.5 +2.0 +1.0 +1.0 MAX UNITS mA mA mA mA mA mA mA mA mA 4 5 5 6 6 NOTES 1, 2, 5 1, 2, 6 1, 2, 3
NOTES:
1) 2) 3) 4) 5) 6) 7)
CLKX = CLKY = 1.544MHz; MCLK = 10MHz Outputs open; inputs swinging full supply levels. Both channels in idle mode. XOUT and YOUT are tri-stated. Applies only to 5V device. Applies only to 3V device (DS2165QL). CLKX, CLKY, MCLK VIH MIN = 2.4V
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DS2165Q
PCM INTERFACE, AC ELECTRICAL CHARACTERISTICS
(VDD = 5V 10%, TA = 0C to +70C; VDD = 3.0V + 20% - 10% for DS2165QL) PARAMETER CLKX, CLKY Period CLKX, CLKY Pulse Width CLKX, CLKY Rise Fall Times Hold Time from CLKX, CLKY to FSX, FSY Setup Time from FSX, FSY High to CLKX, CLKY Low Hold Time from CLKX, CLKY Low to FSX, FSY Low Setup Time for XIN, YIN to CLKX, CLKY Low Hold Time for XIN, YIN to CLKX, CLKY Low Delay Time from CLKX, CLKY to Valid XOUT, YOUT Delay Time from CLKX, CLKY to XOUT, YOUT Tri-stated SYMBOL tPXY tWXYL tWXYH tRXY tFXY tHOLD tSF tHF tSD tHD tDXYO tDXYZ 0 50 100 50 50 10 20 150 150 MIN 244 100 10 20 TYP MAX 3906 UNITS ns ns ns ns ns ns ns ns ns ns 2 2 2 2 2 3 2, 3, 4 NOTES 1
NOTES:
1) Maximum width of FSX and FSY is one CLKX or CLKY period (except for signaling frames). Maximum operating frequency is guaranteed by design and is not a tested parameter. 2) Measured at VIH = 2.0V, VIL = 0.8V, and 10ns maximum rise and fall times. 3) Load = 150pF + 2 LSTTL loads. 4) For LSB of PCM or ADPCM byte.
MASTER CLOCK/RESET, AC ELECTRICAL CHARACTERISTICS
(VDD = 5V 10%, TA = 0C to +70C; VDD = 3.0V + 20% - 10% for DS2165QL) PARAMETER MCLK Period MCLK Pulse Width MCLK Rise/Fall Times
RST
SYMBOL tPM tWMH, tWML tRM, tFM tRST
MIN
TYP 100
MAX
UNITS ns
NOTES 1
45
50
55 10
ns ns ms
Pulse Width
1
NOTES:
1) MCLK = 10MHz 500ppm
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DS2165Q
SERIAL PORT, AC ELECTRICAL CHARACTERISTICS
(VDD = 5V 10%, TA = 0C to +70C; VDD = 3.0V + 20% - 10% for DS2165QL) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES SDI to SCLK Setup SCLK to SDI Hold SCLK Low Time SCLK High Time SCLK Rise and Fall Time CS to SCLK Setup SCLK to CS Hold CS Inactive Time SCLK Setup to CS Falling tDC tCDH tCL tCH t R , tF tCC tCCH tCWH tSCC 50 250 250 50 55 55 250 250 100 ns ns ns ns ns ns ns ns ns 1 1 1 1 1 1 1 1 1
NOTES:
1) Measured at VIH = 2.0V, VIL = 0.8V, and 10ns maximum rise and fall times.
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DS2165Q
Figure 13. PCM INTERFACE AC TIMING DIAGRAM
Figure 14. MASTER CLOCK/RESET AC TIMING DIAGRAM
Figure 15. SERIAL PORT AC TIMING DIAGRAM
Note: SCLK can be either high or low when CS is taken low.
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DS2165Q
28-PIN PLCC
DIM A A1 A2 B B1 C D D1 D2 E E1 E2 L1 N e1 CH1
INCHES MIN 0.165 0.090 0.020 0.026 0.013 0.009 0.485 0.450 0.390 0.485 0.450 0.390 0.060 28 0.042 MAX 0.180 0.120 -- 0.033 0.021 0.012 0.495 0.456 0.430 0.495 0.456 0.430 -- -- 0.048
0.050 BSC
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